The present invention relates to a system for enabling non-volatile memory to execute code while operating as a data storage device.
The primary usage of non-volatile memory is for code execution. In the market of non-volatile code storage memory, flash memory is replacing the ROM various families (ROM, PROM, EPROM, EEPROM) due to its better cost-structure, ease of manufacturing and high densities. Flash is commonly used both as a stand-alone device and as embedded memory. The competition in this market concentrates on condensing the bits of information in a smaller silicon area in order to reduce the cost of the devices. The most common flash type used for code execution is known as NOR Flash. The NOR Flash enables random access to each of its addresses and hence enables to execute code from it. For this reason the NOR Flash is known as an XIP memory, where XIP stands for eXecutable In Place.
While we discussed so far the usage of flash memory for code execution, another emerging market for flash memory is starting to grow and become dominant—the data storage market. Data storage applications require a file system management on the flash memory. Flash memory used for data storage is called a Flash disk and is composed of H/W (flash memory) and a S/W package (file system management, OS interface etc.).
Modern applications usually require flash memory for both code execution and data storage. Today, most architectures use separated devices (or sets of devices) for each functionality. It is very desirable to use the same device (single device) to store both the data and the code of the application. The main benefits are:
reducing real estate requirements, chip count, silicon size and power consumption.
The following scenario illustrates the main problem with this approach:
lets assume that there are two tasks running under the OS in the application.
The first task (T1) is the data storage driver task. It is responsible of storing all the application data on the flash memory. The second task (T2) is some code which is executed from the flash memory (the same flash memory, of course).
The scenario begins with T1 issuing an erase command to some area of the flash memory, as part of the data management requirements. Typical erase time of NOR Flashes is 1 sec. During this period of time (within this 1 sec), OS gives T2 a time slot and T2 starts executing code from the flash memory. At this moment the operation will fail and cause the whole application to fail. The reason is that the flash memory is not available for read operations (e.g., execution of code) while it's busy erasing/programming another section. The OS and T2 are unaware of the fact that the flash isn't available now. The OS and T2 expect that the code stored on the flash will always be available for execution, but this is not the case. As explained above, there are many cases when the flash is not available for execution of the stored code. In fact—it will be unavailable every time it's busy erasing/programming sections following T1 requests.Known Solutions:1. Using two devices, one for data storage and the second as code storage (XIP). As mentioned above, this is the most common architecture that is in use today. See FIG. 1 for a graphic description of this solution.This solution has drawbacks of higher real estate requirements, chip count, silicon size and power consumption.2. Using a single device with multi-bank architecture, which can be simultaneously accessed for read and erase/program. Several flash vendors have started to offer flash devices with multi-bank (usually dual-bank) architecture. With this approach the real estate requirements are reduced and also the chip count is reduced to one. The disadvantage of this solution is the overhead of the silicon (due to the multi-bank design). The estimated cost overhead of this design over a regular design is 30%, so basically one has to pay for the additional functionality with silicon. This solution gains popularity only in real-estate-critical applications, because otherwise it is cost prohibitive. See FIG. 2 for a graphic illustration of this solution.3. Using a single device with a special system S/W that controls and schedules all the tasks of the system, for example, in Intel's PSM. This solution uses the S/W commands of suspend and resume of the flash in order to enable the dual functionality of the device. With this solution the problem of unawareness is solved, but the cost is the complicated integration. This requires a solution to be tailored specifically for every CPU and/or OS. The special system S/W is added to the OS and controls and schedules all tasks and interrupts. The time of integration and development of this solution is excessively long since the complexity is high. In addition this is a very intrusive approach, which might suit some niche markets.
There is thus a widely recognized need for, and it would be highly advantageous to have, a system that can enable true simultaneous usage of non-volatile memory for both code execution and data storage.
The present invention provides another approach to solve the problem of one non-volatile (flash) device (or a set of devices) used both for data storage/processing and code execution. The solution enables proper functionality of both usages and in particular will enable execution of code from the flash at any time, including times when the flash is busy erasing/programming some sections.
The present invention is of a hardware application that enables flash memory devices to be both created and operated in an efficient manner, enabling usage of Flash memory for code execution and data storage/processing concurrently.